The present invention relates, generally, to non-volatile memory devices and fabrication processes and, more particularly, to inter-level-dielectric (ILD) structures for EEPROM memory devices and to methods of fabrication.
Non-volatile memory devices are both electrically erasable and programmable. Such devices retain data even after the power to the device is terminated. One particular type of non-volatile memory device is the EEPROM device. In a flash EEPROM device, programming and erasing is accomplished by transferring electrons to and from a floating-gate gate electrode through a thin dielectric layer, known as a tunnel oxide layer, located between the floating-gate electrode and the underlying substrate. Typically, the electron transfer is carried out either by hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating-gate electrode by a control-gate electrode, which can be a doped region in the substrate. The control-gate electrode is capacitively coupled to the floating-gate electrode, such that a voltage applied to the control-gate electrode is coupled to the floating-gate electrode.
EEPROM cells are extensively used in programmable logic devices (PLDs). EEPROM cells used in PLDs can have a two-transistor design or a three-transistor design. A three transistor EEPROM cell, for example, includes a write transistor, a read transistor, and a sense transistor. In a two-transistor device, the functions of read and sense transistors are combined into a single transistor. To program PLD EEPROMs, a high voltage Vpp+ is applied to the gate electrode of the write transistor and a relatively low Vpp is applied to the drain (bit line contact) of the write transistor. The voltage applied to the write transistor gate electrode turns the write transistor on allowing the voltage applied to the bit line to be transferred to the source of the write transistor. Electrons on the floating-gate electrode are drawn from the floating-gate electrode to the source of the write transistor, leaving the floating-gate electrode at a high positive potential. The application of such high voltage levels is a write condition that results in a net positive charge being stored in the EEPROM cell.
To erase the EEPROM cell, a voltage Vcc is applied to the gate of the write transistor and ground potential is applied to the bit line and a high voltage Vpp+ is applied to the control-gate electrode. Under this bias condition, the high voltage applied to control-gate electrode is coupled to the floating-gate electrode and the EEPROM cell is erased by the transfer of electrons from the substrate to the floating-gate electrode.
To effectively store information, electrical charge must remain on the floating-gate electrode after a programming operation. EEPROM devices are typically constructed as memory cells packed closely together in a memory array. As the EEPROM memory cell and neighboring cells are continually programmed and erased, the active cell is subjected to high voltage levels, for example Vpp+ is typically at least about 12 volts. Neighboring cells also experience a high electric field during the program and erase operations of a selected cell.
During high voltage operation, there is a tendency for the charge on the floating-gate to bleed off, or leak, as a result of exposure to high electric fields. When charge leaks from the floating-gate, the memory cell will lose its stored data. Good data retention is a key reliability characteristic of a non-volatile memory device. As memory devices are scaled to smaller and smaller dimensions, good data retention becomes more difficult achieve. This is due, in part, to the high packing density of the memory cells and to the relatively small size of the floating-gate charge storage layer. Better data retention can be obtained in advanced memory devices by improving the overlying electrical insulation layers that reside between the charge storage elements and the electrical interconnect layers. Accordingly, a need exists for an EEPROM device and fabrication process to produce an EEPROM device having improved data retention characteristics.
An EEPROM memory device and fabrication process is provided for an EEPROM memory device having improved data retention characteristics. In one aspect of the invention, an inter-level-dielectric layer is provided that is fabricated using a two-step deposition process. An annealing process is carried out between the two deposition steps to improve the electrical insulation characteristics of the inter-level-dielectric (ILD) layer. Additionally, the ILD layer is doped to improve its step coverage and annealing characteristics. In a further aspect of the invention, the first deposited layer is etched back prior to depositing the second layer. In a preferred embodiment of the invention, the first deposited layer is doped with boron and phosphorous, and the second deposited layer is doped with phosphorous. An EEPROM device fabricated in accordance with the invention includes a floating-gate transistor having stable threshold voltage values, even when subjected to high temperature baking over a prolonged period of time. EEPROM devices fabricated in accordance with the invention also exhibit high. endurance and show little high voltage leakage.
In one aspect, the invention includes providing a substrate having a high voltage device layer thereon. A first oxide layer is deposited on the device layer and the first oxide layer is thermally treated. A second oxide layer is then deposited to overlie the first oxide layer after thermally treating the first oxide layer. The first oxide layer is preferably deposited using an alkyl silicon source gas, such as tetraethylorsilane and the like.
In another aspect of the invention, an EEPROM memory device is provided having a floating-gate transistor that is fabricated to have a specified threshold voltage. A dielectric liner overlies the floating-gate transistor. An annealed, boron-doped oxide layer overlies the dielectric liner. A second oxide layer overlies the annealed, boron-doped oxide layer.